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Low temperature 3D wafers bonding for high speed and high density microchip applications


Future computer chips operating with tens of GHz speed (sub THz) and Tera bits memory would require the stacking of microchips and memories in a three-dimensional (3D) architecture. IGERT trainee Tom Parker and the research team including IGERT co-PI Toh-Ming Lu have discovered a new technique to glue two wafers at low temperature and potentially can be a game-changing technology in 3D integration of circuits. Stacking of microchips requires low temperature bonding lower than 400°C. This is because the materials in the microchips cannot sustain high temperature excursion without being damaged. Since Cu interconnect is used in high performance microchips, it is desirable to use Cu itself as the bonding material to form a 3D architecture. However, the bulk melting temperature of Cu is over 1000°C and it is not easy to bond two Cu films face-to-face at a low temperature. We found that if the Cu can be made into very small rod-like structures, on the order of a few nanometers to tens of nanometers in diameter, they can be fused together at below 400°C 1. Nanoscale materials have a large surface area to volume ratio. The high mobility of surface atoms allows them to fuse together and enhances grain growth at low temperatures during bonding. As illustrated schematically in the figure, two wafers were coated with Cu nanorod layers (upper right figure) as an adhesive and then were bonded together (lower right) at less than 400°C under a uniform down force of 10 kN (equivalent to 0.32 MPa across 200 mm diameter wafers) for 1 hour for the bonding process. The Cu grains have grown entirely over the original Cu nanorod bonding interface, leading to a homogeneous structure shown in the SEM image (lower left inset).

Address Goals

Tom Parker, a graduate student in multidisciplinary engineering program and an IGERT trainee, learned the cutting edge technique of growing Cu nanorod structures for the bonding experiment. Nanometer-sized Cu rod arrays are produced by vapor deposition at an oblique angle, which is conducted with an obliquely incident flux that enhances atomic shadowing and creates an inclined columnar microstructure under the condition of limited adatom diffusion. The structure develops through a competitive growth. There is a distribution in the nanorod height. The taller Cu nanorods shade the growth fronts of shorter rods. The nanorods that win this competitive growth process expand their diameters and eventually take over the space of the losing rods. Eventually a saturation or equilibrium nanorod diameter is achieved. Mr. Parker has mastered this very powerful technique to address the area of national needs, in this case, the fundamental understanding of science of thin film growth and the creation of 3D super fast and high density microchip technology.

1 Pei-I Wang, Sang Hwui Lee, Thomas C. Parker*, Michael D. Frey, Tansel Karabacak, Jian-Qiang Lu, and Toh-Ming Lu, “Low Temperature Wafer Bonding by Copper Nanorod Array”, Electrochemical and Solid-State Letters, 12 (4), H138-H141 (2009).